1. Field of the Invention
The present invention relates to a method of generating a mask for fabrication of a physical layer of an integrated circuit. More particularly, the present invention relates to a method of generating such a mask for fabrication of an integrated circuit which comprises multiple physical layers.
2. Description of the Prior Art
The fabrication of a contemporary integrated circuit is a complex process involving many stages and participants. Typically, the designer of an integrated circuit sets out a definition of the integrated circuit comprising a layout design for each physical layer of the integrated circuit, wherein a contemporary integrated circuit typically comprises many physical layers (e.g. multiple metal layers, polysilicon layers, diffusion layers, via layers, contact layers and so on). This definition of the integrated circuit (for example in the form of a gds2 file) is then provided to a dedicated manufacturing facility which has the ability to turn this computer-generated multi-layer design of an integrated circuit into the fabricated integrated circuit itself.
The fabrication process itself is highly specialised and complex, but of relevance here is the mask generation procedure which transforms the designed layout of a given layer of the integrated circuit into a photolithographic mask to be used in the photolithography procedure of using incident light filtered by the mask to etch the desired design layout for that given layer of the integrated circuit.
As the process scales at which contemporary integrated circuits are generated get ever smaller, it is known that the layout of the mask for a given layer of the integrated circuit is not generated as having an identical layout to the desired layout of the physical structure of that layer, but rather the mask is modified (for example according to optical proximity correction techniques) to ensure that the physical structures which remain after the photolithography has taken place will reliable reflect the designer's intention. Such techniques are necessary because of, for example, diffraction effects resulting from the scale of the apertures in the mask being of a comparable scale to the wavelength of the incident light.
It is also known for an integrated circuit to have programmable subcomponents, wherein each programmable subcomponent of the integrated circuit can take a number of logical configurations in dependence of the position of one or more physical structures in a given physical layer of the integrated circuit within that subcomponent. For example, it is known to construct a read-only memory (ROM) within an integrated circuit, wherein the logical value stored within each ROM bit cell is determined by the selected positions of vias within that ROM bit cell which connect a first metal layer to a second metal layer.
In the case of an integrated circuit comprising programmable subcomponents, it is also known to be the case that the integrated circuit is designed, taped out as a finalised layout of each physical layer of the integrated circuit and provided to the foundry for generation of the masks for each physical layer of the integrated circuit, but it is then found that the programming of the programmable subcomponents should be amended. For example in the case of an integrated circuit providing a ROM, it may be desired to change the programmed content of the ROM. Accordingly the layout of the physical structures in the relevant layer (e.g. via layer) of the integrated circuit is then reconfigured and the foundry is required to regenerate the mask for that particular layer.